Design of Semi-Static SET Flip-Flop for Low Power and High Performance Applications
نویسندگان
چکیده
The paper proposed a new design for implementing semi-static flip-flop for low power and high performance applications. In this work, comparative analysis of six existing flip-flop designs along with the proposed design is made. The proposed design has better power, delay and PDP than the existing architectures. All simulations are performed on TSpice using BSIM models in 130 nm process node. The simulation results show that for all supply voltages, all clock frequencies and all data activities, the proposed flip-flop has the better power consumption than all the six existing flip-flops discussed in this paper. The proposed flip-flop also shows the second lowest PDP and the second shortest delay. Keywords— Single edge triggered, PDP, Energy efficient, High performance
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